Search - frequency divider

[VHDL-FPGA-Verilog] phase_add

Description: 分频器，实现任意频率的分频，只需修改频率控制字,已经经过多次验证-Divider to achieve any frequency divider, simply modify the frequency control word, has been repeatedly verified
Platform: | Size: 1024 | Author: 岁月 | Hits:

[VHDL-FPGA-Verilog] clk1hz

Description: 分频电路将电路分频为1赫兹可用于FPGA实验-Frequency divider circuit is a circuit that can be used in FPGA Hz
Platform: | Size: 1024 | Author: Frozen | Hits:

[source in ebook] div_freq

Description: 分频器，把一个特定的频率进行分频，从而得到自己想要的频率-Frequency divider, a specific frequency divider, you want to get the frequency
Platform: | Size: 459776 | Author: tina | Hits:

[Other] DivFrec

Description: Employ IP cores in VHDL to describe some functions Module digital clock manager , in this case to create a frequency divider
Platform: | Size: 2048 | Author: Mario | Hits:

[VHDL-FPGA-Verilog] fp_prj

Description: 分频器，Verilog语音编写，quartus仿真过，可以利用使蜂鸣器发生-Frequency divider, Verilog speech writing, quartus simulation, can make use of the buzzer
Platform: | Size: 204800 | Author: 孟稳 | Hits:

[Algorithm] frequency_divider

Description: Frequency Divider vhdl source code with test bench
Platform: | Size: 1024 | Author: kd | Hits:

[Other] frequency-divider

Description: 利用FPGA实现分频器功能并完成LED数码管静态和动态显示-Using FPGA to achieve crossover features and complete LED digital control static and dynamic display
Platform: | Size: 1024 | Author: 李程祥 | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 通过FPGA设计实现的分频模块，仿真可以通过，适合初学者学习。-Through the FPGA design of frequency divider module, simulation can be passed, for beginners to learn.
Platform: | Size: 301056 | Author: wanchun | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 对m序列进行2ASK调制包含分频器 m序列发生器正弦信号发生器二路选择器4个模块-process m sequence with 2Ask includes frequency divider, m sequence generator, sine signal generator and MUX
Platform: | Size: 1198080 | Author: changquan | Hits:

[Algorithm] Frequency_divider

Description: 奇数分频器，通用分频器，占空比1:1分频器，占空比非1:1分频器-Frequency divider
Platform: | Size: 293888 | Author: weiminxiongqi | Hits:

[ARM-PowerPC-ColdFire-MIPS] FENPIN48

Description: FPGA分频器，利用计数器计数，将外部晶振的48MHZ时钟分频为1MHZ-48M frequency division 1M frequency divider
Platform: | Size: 38912 | Author: 郭震 | Hits:

[Software Engineering] clk_divR

Description: frequency divider into reglable frequence
Platform: | Size: 1024 | Author: bakar132 | Hits:

[VHDL-FPGA-Verilog] VHDL-Code-and-TestBench-Code

Description: 实现了三个功能电路的程序：时钟分频电路；移位寄存器；序列检测器。-Including three parts:frequency divider shifting register sequential detector
Platform: | Size: 100352 | Author: jimmy020 | Hits:

[VHDL-FPGA-Verilog] sin

Description: 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter shaping filter with FIR, finally get the output.
Platform: | Size: 6779904 | Author: 猪头 | Hits:

[Other] fenpin

Description: 通用整数分频器，可以分频占空比为1:1，也可以为任意占空比-General integer frequency divider, can divide frequency and duty ratio of 1:1, also can be for any duty ratio
Platform: | Size: 1024 | Author: 春春 | Hits:

[VHDL-FPGA-Verilog] diviseurFrquence50MhzTo1hz

Description: this file about frequency divider 50 MHz to 1 Hz used in 7-segment display
Platform: | Size: 422912 | Author: gps | Hits:

[VHDL-FPGA-Verilog] divider-achieved-by-verilog

Description: 该代码用Verilog语言实现了分频功能，主要实现对输入时钟的54分频，已通过仿真验证。-The code in Verilog realize the crossover functions, the main achievement of the input clock frequency of 54 minutes, has been verified by simulation.
Platform: | Size: 2048 | Author: daruili | Hits:

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[VHDL-FPGA-Verilog] phase_add

[VHDL-FPGA-Verilog] clk1hz

[source in ebook] div_freq

[Other] DivFrec

[VHDL-FPGA-Verilog] fp_prj

[Algorithm] frequency_divider

[Other] frequency-divider

[VHDL-FPGA-Verilog] fenpin

[VHDL-FPGA-Verilog] fenpin

[Algorithm] Frequency_divider

[ARM-PowerPC-ColdFire-MIPS] FENPIN48

[Software Engineering] clk_divR

[VHDL-FPGA-Verilog] VHDL-Code-and-TestBench-Code

[VHDL-FPGA-Verilog] sin

[Other] fenpin

[VHDL-FPGA-Verilog] diviseurFrquence50MhzTo1hz

[VHDL-FPGA-Verilog] divider-achieved-by-verilog

[VHDL-FPGA-Verilog] 4.5fenpingqi

[Voice Compress] fenpinqi

[VHDL-FPGA-Verilog] UD_DIVDER

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